1. Field
Various features relate to integrated circuits (ICs), and more particular/to electrostatic protection for stacked multi-chip integrated circuits.
2. Background
The ever increasing demand for smaller, lighter, and faster portable electronic devices, such as mobile phones and laptop computers, has encouraged the electronics industry to create circuit components having greater capacity, performance, and smaller dimensions. For example, portable devices may now contain integrated circuit (IC) packages having two or more semiconductor dies stacked vertically and encased within the same molding compound of the IC package. Such multi-chip IC packages may be commonly referred to as “chip stack multi-chip modules” (MCM). According to one technique called “through silicon stacking” (TSS), the vertically stacked multiple semiconductor dies are electrically coupled to one another using through substrate vias (TSVs). TSVs are electrical conductors typically made of metal that pass vertically through the thickness of a die's substrate such that one end is exposed at a back side surface of the die substrate, and another, opposite end is electrically coupled to the active surface of the die.
FIG. 1 illustrates, a schematic, cross-sectional side view of a TSS MCM 100 found in the prior art. The MCM 100 includes a plurality of semiconductor dies 102a, 102b, 102c that are electrically coupled to one another using TSVs 104a, 104b, 104c. The top die 102a has an active surface 106a that includes a plurality of integrated circuit components (e.g., transistors, capacitors, inductors, resistors, etc.), and a back side surface 108a. The TSV 104a is electrically coupled to the active surface 106a and runs through the thickness of the die's 102a substrate. Similarly, the middle and bottom dies 102b, 102c each have active surfaces 106b, 106c and back side surfaces 108b, 108c. The middle die's TSV 104b is electrically coupled to the middle die's active surface 106b, and the bottom die's TSV 104c is electrically coupled to the bottom die's active surface 106c. 
The TSVs 104a, 104b, 104c have contact pads 110a, 110b, 110c at one end and contact pad receivers 105a, 105b, 105c at an opposite end. Each dies' active surface 106a, 106b, 106c may be electrically coupled to its respective TSV 104a, 104b, 104c. The contact pads 110a, 110b, 110c are exposed at the dies' front side active surfaces 106a, 106b, 106c, and the contact pad receivers 105a, 105b, 105c are exposed at the dies' back side surfaces 108a, 108b, 108c. The contact pads 110a, 110b, 110c are metal “microbumps” and the contact pad receivers 105, 105b, 105c may be metal indentations on the dies that have a corresponding curvature to receive and mate to the microbumps 110a, 110b, 110c. 
The top die's contact pad 110a is physically and electrically coupled to the middle die's contact pad receiver 105b, and the middle die's contact pad 110b is physically and electrically coupled to the bottom die's contact pad receiver 105c. In this fashion, the dies' active surfaces 106a, 106b, 106c, are electrically coupled to one another through the vias 104a, 104b, 104c. 
The bottom die 102c is physically and electrically coupled in a flip chip fashion to a package substrate 112 (e.g., laminate substrate, metal based substrate, such as copper based substrate, etc.) with an underfill and/or epoxy 115. The package substrate 112 may include multiple layers having a plurality of interconnections not shown) there between. The interconnections in turn may be electrically coupled to a plurality of soldering balls 114 that form a ball grid array (BGA) that the MCM 100 uses to electrically couple to a printed circuit board (not shown). The components of the MCM 100, including the dies 102a, 102b, 102c, the TSVs 104a, 104b, 104c, and at least a portion of the substrate 112 may be encased in a molding compound 116.
FIG. 2 illustrates the process of electrically and physically coupling the top die 102a to the middle die 102b during manufacturing of the MCM 100. In the illustrated example, the molding compound 116 (See FIG. 1) has been removed to show how the top die 102a is placed onto the middle die 102b (the three directional arrows in FIG. 2 illustrate the motion of the top die 102a toward the middle die 102b). During this process, the top die 102a is moved close to the middle die 102b, and stacked on top such that the contact pad 110a of the top die 102a mates with the contact pad receiver 105b of the middle die 102b. However, sometimes the top die 102a may have an electrostatic potential that is substantially different (e.g. much greater or much less) than the middle die 102b, which may be grounded. When the two dies 102a, 102b get sufficiently close (e.g., upon contact), an electrostatic discharge (ESD) event (i.e., static electricity) may be triggered such that a relatively large amount of current momentarily flows through the TSV 104b of the middle die 102b. Without proper ESD protection circuitry, sensitive IC components (such as buffer circuit transistors) located on the middle die's active surface 106b that are electrically coupled to the TSV 104b may be damaged from the ESD event. In some cases, circuitry located on the active surface 106a of the top die 102a may also be damaged. Similarly, other dies within the MCM 100 are also prone to such ESD harm, including the bottom die 102c when the middle die 102b is electrically and physically coupled to the bottom die 102c. 
FIG. 3 illustrates a schematic of an ESD protection circuit 300 found in the prior art that may be coupled to the middle die's TSV 104b to protect the middle die's 102b circuitry 310 from ESD damage. The ESD protection circuit 300 features diodes 302, 304 that form a shunt which bypasses the ESD current away from the sensitive circuitry 310, which may be, for example, an output signal buffer.
Although the ESD protection circuit 300 may be effective in protecting the output signal buffer 310 from ESD damage, the ESD protection circuit 300 has notable disadvantages. For example, the diodes 302, 304 may occupy significant silicon/die area due to their relatively large size that is needed to accommodate the high ESD current flow. Moreover, the diodes 302, 304 create parasitic effects at the TSV 104b output node 306, including parasitic capacitance and/or inductance. To compensate for these parasitic effects, the buffer 310 size may have to be larger so that it can sufficiently drive the output signal at the output node 306. A larger buffer 310 consumes more power and also takes up more active silicon/die area. Therefore, the silicon/die area devoted to the ESD protection circuitry 300 directly (e.g., diode 302, 304 component area) and indirectly (e.g., larger buffer 310) uses active surface area that may otherwise be used for other IC components.
Thus, there is a need for advanced ESD protection circuits that adequately protect dies of an MCM without suffering from the aforementioned size and power consumption issues.